This invention relates to digitally encoding and decoding electrical signals, particularly signals representative of music. In delta modulating and other similar systems, the digitally encoded signal stream (1's and 0's) represents the slope of each segment of the analog signal. A digital 1 means the analog slope is positive, and the decoder reconstructs the analog signal by increasing it a predetermined amount. A digital 0 causes the decoder to decrease the analog signal by the same amount. Thus, the reconstructed analog signal appears as a series of positively or negatively-sloped segments. The relative preponderance of 1's or 0's in the digital signal stream indicates whether the analog signal is rising, falling, or not changing.
The digital signal is encoded from an analog input by comparing, at each clock interval, the reconstructed (decoded) analog signal (the most recent output of the decoder, representative of a past value of the input to the encoder) with the present value of the input and generating a 0 if the input is less than the reconstructed signal and a 1 if the input is greater.
The major difficulty with such systems has been in choosing the amount by which to increase or decrease the reconstructed signal at each interval, i.e., the magnitude of the decoding slope. If the decoding slope chosen does not roughly match the slope of the input, there will be noticeable quantization noise or error in the reconstructed output. In systems where the decoding slope is held constant, the input can only accurately be encoded over a narrow range of amplitudes.
To overcome the limitations of using a constant decoding slope, the prior art has provided circuits for varying the size of the decoding slope in relation to the magnitude of the input. Such systems are often referred to as having adaptive delta modulation.
For example, in DeFreitas U.S. Pat. No. 4,254,502 circuitry is provided for operating on the digitally-encoded signal to generate what is called a reference signal that prescribes the decoding slope. A shift register and associated logic detects repetitions (or coincidences) of the same digital state (e.g., two 0's or two 1's), and supplies an output to a filter and detector circuit that, in turn, generates the reference signal. The magnitude of the signal supplied to the filter and detector is dependent on the number of coincidences in the digitally-encoded signal. If as many as four coincidences occur, indicating the need for a rapid increase in decoding slope, a positive feedback path is switched on to connect the output of the filter and detector circuit to its input.